Course: Intel tools

Intel development / HPC tools

HPC2N and Intel would like to welcome you to a two day course, consisting of training in the following Intel tools: Composer XE, Advisor XE, and VTune Amplifier XE, as well as an overview of using OpenMP 4.

This training will concentrate on Intel tools for single node optimization. A strong focus is on hands on labs done on Intel provided laptops. Participants get the chance to test Intel tools on provided codes samples to investigate and improve vectorization and OpenMP scalability. A few additional predefined examples from previous cluster runs will give an impression on how this analysis looks like for realistic codes..

Preliminary schedule


  • Short Introduction to Intel tools used in this course
  • Compiler, Vectorization and use of Intel® Advisor XE
  • Applying Advisor XE directly on the Compiler Vectorization examples. This will help to relate Compiler optimization output and Advisor analysis.
  • Basic usage of Intel® VTune™ Amplifier XE
  • Lab time for VTune and unfinished previous labs.

Day 2

  • OpenMP4: Using OpenMP tasks and other new features of OpenMP
  • Advisor XE: Lab time for more involved examples. Participants can bring their own codes
  • VTune Amplifier XE. OpenMP analysis including hybrid MPI/OpenMP codes
  • VTune Amplifier XE advanced analysis: Using event based sampling for memory and other architecture related issues.
  • Lab time with more hands on to finish previous labs or following any new ideas that came up during the work shop.

Note that bringing your own code is optional. There will be lab codes to work on too.

Participation is free. Lunch and coffee will be provided.

Intel will bring preconfigured laptops for you to borrow during the hands-ons.

Prerequisites: The participants are expected to have a basic knowledge of programming in C or Fortran, and basic usage of compilers. In addition, they should have basic knowledge in parallel programming.

Instructors: Intel trainers

Time and date: 9:00 - 17:00, 18-19 May, 2016.

Location: MIT-Huset, room MA176 (18 May), MA166 (19 May)

Deadline for registration: 11 May 2016.

Please register using this form. All fields are mandatory.


Updated: 2024-04-17, 14:47